1. Field of the Invention
The present invention relates phase-locked loop (PLL) frequency synthesizers and, in particular, to lock detectors for detecting when frequency and phase of the output clock signal generated by the PLL matches that of an input clock signal.
2. Description of the Related Art
Frequency synthesizer circuits are often used to generate an output signal whose frequency bears a specified relationship to the frequency of an input reference signal. This may be used to generate an output clock signal having an accurate frequency, for example, based on an input clock signal having a known frequency.
A common form of frequency synthesizer is a phase-locked loop based circuit (PLL). A PLL receives an input signal and produces an output signal of substantially the same frequency with a predetermined phase relation to the input signal. A PLL can be used wherever it is necessary to synchronize the phase and/or frequency of two signals. In a typical communications type application, a PLL is used to synchronize a local oscillator to the frequency (and/or phase) of an incoming data signal. PLLs are widely used in space communications, for example, for coherent carrier tracking and threshold extension, bit synchronization, and symbol synchronization.
In one application, a PLL may be used to tune a high frequency local oscillator to a separate, more stable, lower-frequency local oscillator. For example, a very high frequency signal may be necessary for synchronizing to an incoming radio frequency signal at, for example, 800 MHz. Crystal oscillators are very stable and accurate, but typically do not operate at high enough frequencies to be used directly for high radio frequency applications. Thus, a high frequency voltage controlled oscillator (VCO) may be utilized, which generates the desired high frequency very precisely, by placing the VCO in a phase locked loop with a crystal oscillator.
A PLL typically comprises a phase and/or frequency comparator (e.g., a phase detector [PD] or phase/frequency detector [PFD]), which receives and compares an external input signal (or a divided version of this signal, which is used as a reference signal) to the output signal generated by a VCO (or a divided version of this signal), a "charge pump" for receiving the output of the PD or PFD, and a low pass "loop" filter which receives the output of the phase comparator and provides an output control voltage to the VCO. A common form of VCO for use in a PLL is a ring oscillator that employs a series of delay elements to provide the desired frequency range of operation.
The PFD forms a difference signal by comparing the external input signal and the VCO signal. In one type of PFD, the difference signal consists of UP (fast) and DOWN (slow) pulse signals, which are applied to the charge pump. The charge pump generates charge based on the UP or DOWN signals, which charge is integrated by the loop filter to produce a DC control voltage. This DC control voltage controls the output frequency of the VCO. When the frequency and phase of the signals compared by the PFD are substantially identical, the PLL is said to be in a state of lock (both frequency and phase lock). Because of the closed loop nature of a PLL and the negative feedback employed, the output frequency of the VCO is maintained to closely match the frequency of the reference input signal. A PLL may be used, therefore, to cause the output signal of the VCO to be locked to a stable reference frequency. For this reason, a PLL is often employed to generate an output reference signal, at a desired frequency, that is frequency and phase locked relative to some input reference signal.
Typically, the output clock signal and the input clock signal are each multiples of some common, lower frequency. For example, a 10 MHz input clock signal and a 25 MHz output clock signal are both multiples of 5 MHz. Thus, in the PLL, the 10 MHz input clock signal may be divided by 2 to provide a "common denominator" reference signal 5 MHz signal, and the 25 MHz output clock signal may be divided by 5 to provide a feedback signal of nominal frequency 5 MHz, for comparison by the PFD. (Alternatively, the VCO may itself generate a higher frequency, such as 50 MHz, which is divided by 2 to provide the 25 MHz output clock signal, and divided by 10 to provide the 5 MHz feedback signal.)
PLLs can take a significant but unspecific and unpredictable number of input clock cycles to achieve the lock condition. There is therefore a need to know whether and when lock has occurred, or when it is safe to assume that the PLL has achieved lock. For example, this determination can be used to change certain loop parameters to ensure narrow loop tracking in order to reject noise and other interfering signals. Thus, there is a need for lock detection circuitry to detect when the PLL is locked, i.e. when the frequency and the phase of an output signal matches the frequency and phase of an input signal. PLLs and lock detection techniques are described in further detail in Floyd Martin Gardner, Phaselock Techniques, 2nd ed. (Wiley 1979); Roland E. Best, Phase-Locked Loops (McGraw-Hill 1993); C. R. Hogge, "A Self Correcting Clock Recovery Circuit," Journal of Lightwave Technology, Vol. LT-3, No. 6 (December 1985), pp. 1312-1314.
One approach is to assume some predetermined, finite, maximum lock time during which the PLL should have locked. This maximum lock time is usually specified very conservatively, often five or more times longer than the typical lock time. A lock detect circuit may simply count this specified maximum lock time and then indicate the lock condition exists after the specified maximum lock time has elapsed. One disadvantage of this approach is that system time is wasted when lock occurs earlier than the maximum lock time, which is most of the time. Another disadvantage is that if lock is subsequently lost, or if lock is for some reason not achieved by the maximum lock time, there is no indication of the loss of lock and, indeed, there is an erroneous lock indication.
Another technique employs two counters, one from the input clock and one from the output clock. After a fixed number of the input clock cycles (a "test cycle"), the count of the output clock counter is examined to determine if it is the correct value (usually.+-.one count or cycle of where the output clock should be after the fixed number of input clock cycles). Such a determination requires knowledge of the desired ratio between the frequencies of the input or reference clock and the output clock. If the output clock counter value is correct (i.e., within the specified degree of tolerance), the circuit is considered to be locked and an output indicator for lock is set. If the value is incorrect, both counters are restarted and the process is repeated. A disadvantage of this approach is that certain conditions can lead to a false lock indication. For example, the output clock may still be wandering but may have an average frequency equal to that of the reference clock, thus yielding the expected counter value, within the acceptable tolerance, even though there is really no lock yet. Alternatively, if there is frequency lock but not phase lock, this technique may indicate a lock before there is both phase and frequency lock. Additionally, the output clock might count to a much higher value than that for the reference clock (because it is higher frequency than the input clock), thereby causing the counter to overflow and start over again, and end up within the expected count range at the end of the test cycle even though the frequency of the output clock is far greater than it is supposed to be.
Yet another approach examines the "closeness" of the clock signal edges at the phase detector input. If the compared edges are nearly coincident for several repetitions (clock cycles), the circuit is considered to be locked and an indicator is set. A disadvantage of this technique lies in its use of analog techniques to accurately time the closeness of the edges. Further, if the loop has a static phase error, the loop may be actually locked but the edge-comparison approach would be unable to detect the lock and would thus (falsely) fail to provide a lock indication signal.
There is a need, therefore, for improved lock detector circuits and techniques for detecting when the PLL has achieved both frequency and phase lock.